1. Field of the Invention
The present invention pertains generally to electrical computers and more particularly to devices and methods of modeling and simulating an electrical circuit.
2. Background of the Invention
Modern electronic chip designers commonly employ functional models in the design and simulation of electronic circuits. A previous method required circuit designers to connect logic symbols representing logic cells to specify a circuit design. Each logic symbol was associated with data defining the functionality of the corresponding logic cell. This method required the designer to be familiar with the functionality associated with the logic cell represented by each logic symbol. After a circuit was specified using the logic symbols, a designer could translate the representation to a gate-level design database or netlist, which would be the basis for simulation.
Using more modern techniques, a designer may specify the functionality of a circuit in a manner similar to specifying the functionality of a software module. Such functional descriptions are typically textual and are specified in a hardware description language (HDL), such as VHDL (VHSIC Hardware Description Language), Verilog Hardware Description Language and the like. Each language has its own syntax, control flow constructs, and other functionality. VHDL is specified by the IEEE Std. 1164-1993, incorporated herein by reference.
Generally, each language provides the ability to "program" the functionality of a design with little or no specific regard to the underlying functionality and structure of the discrete component logic cells. A designer describes the desired functionality of the electronic circuit using the HDL rather than connecting logic symbols as done in older design methodologies. The functional description is in the form of a register-transfer-level (RTL) description, which is readable by a circuit simulator. The hardware simulator allows the designer perform a RTL simulation and verify the functionality of the hardware design in a manner substantially independent of the underlying hardware logic cells.
After the functional design has been simulated and verified, a gate-level design database or netlist may be generated from the VHDL or Verilog program. Technology dependent gate-level models are combined with the technology independent RTL description to generate the gate-level design database or netlist. This process is known as "logic synthesis." The gate-level design database or netlist may then be simulated to verify design functionality using a particular logic cell library in a particular semiconductor technology. The design database or netlist is also used as input to subsequent stages of the design process, such as routing metal interconnections between logic cells using a place-and-route tool and generating mask works required in the semiconductor fabrication process using pattern generation.
A key element of this modern design and simulation process is the initial development of the functional models used to define various logic cells. In gate-level-simulations, the various logic cell models are combined to achieve the HDL-specified functionality of the desired circuit design in a specific cell library and semiconductor technology. For example, a designer may require a Boolean AND function in a desired circuit design. The designer programs AND functionality in a VHDL description of the circuit functionality, and the logic synthesis tool may select an AND logic cell model to achieve this functionality in the gate-level design description. For the purposes of this example, assume the AND function accepts two input operands, performs the Boolean AND operation on the two operands, and provides a single output result of the operation. Accordingly, the logic cell model must be defined to accept two parameters and to generate a single output. In addition, the logic cell model is also associated with functionality information, including the Boolean operation itself, the signal propagation delay from each input to the single output, and other functional characteristics.
The propagation delay characteristics of logic paths within the Boolean AND function are crucial functional features. Specifically, the propagation delay characterizes the time between a signal transition at an input to the logic cell and the resulting signal transition, if any, at the output of the logic cell. Propagation delay information is used to schedule signal transitions during design simulations to ascertain the timing relationships between signals during operation of the circuit.
A circuit in simulation may experience timing mismatches that create unintentional or spurious signal transitions within the circuit. For example, a signal transition may occur at one input of the previously described AND logic cell, quickly followed by a signal transition at the other input of the AND logic cell. In this situation, if each input transition results in a corresponding output signal transition, the output signal will be a narrow pulse. If the pulse width of the output pulse is narrower than a predetermined width, it may be desirable to suppress the narrow output pulse (also called a "glitch") to prevent its propagation to the subsequent input. The technique is called "pulse rejection", and the predetermined width is called a "pulse-rejection period".
Some simulators provide pulse handling functionality in the simulator itself. For example, U.S. Pat. No. 5,091,872, issued to Agrawal, discloses a logic simulator for detecting a spike condition at the output of a simulated gate and producing an "unknown" or undefined output event in response. Likewise, U.S. Pat. No. 4,787,062, issued to Nei et. al., discloses a glitch detection algorithm implemented in a hardware accelerator or simulator.
In contrast, the Verilog Hardware Description Language allows the designer to set an arbitrary pulse rejection parameter within the Verilog description of a logic cell, causing the logic cell to suppress pulses having pulse widths below the specified width during simulation. This capability is an inherent function of the Verilog Hardware Description Language itself and does not require a particular logic cell modeling technique. VHDL, however, does not support arbitrary pulse rejection within the language itself. Instead, VHDL only supports pulse rejection for pulses having pulse widths equaling the propagation delay of the logic cell or, of course, equaling zero. Furthermore, a VHDL-specified design may be simulated within a simulator that does not support arbitrary pulse rejection. Therefore, a need exists to provide an efficient method and device to provide arbitrary pulse rejection functionality in a hardware design specified in VHDL and simulated in a simulator that does not support arbitrary pulse rejection itself.